1. Field of the Invention
The present invention relates to an improvement in the operation of MOS (metal-oxide-semiconductor) memories and, more specifically, to the use of divided bit line isolation within dual sense amplifier constructions.
2. Description of the Prior Art
Research and development in semiconductor technology have produced semiconductor memories with tremendous capacity and performance characteristics. Today, semiconductor memories can be divided into two classes: static memories and dynamic memories. Static memories are not of interest here and will not be discussed. However, an example of a static memory can be found in U.S. Pat. No. 4,402,066, issued to Itoh et al, which discloses an improved static memory circuit having reduced read access time.
FIG. 1 shows a simplified prior art dynamic memory array in which a sense amplifier 10 is flanked by oppositely placed bit lines 50 and 51. The actual circuitry of the sense amplifier 10 is not of concern here and will not be discussed. In the typical dynamic memory shown in FIG. 1, digital data is stored in a matrix of memory cells, each of which has a capacitor for storing a charge corresponding to a logical 1 or 0. A memory cell capacitor C.sub.M is shown for each of the memory cells 100 and 110 in FIG. 1.
The memory cell capacitors C.sub.M are connectable to an associated bit line by an isolation transistor T.sub.M of each of the memory cells 100 and 110. The memory cell isolation transistors T.sub.M of the memory cells 100 and 110 are controlled by word lines 160 and 180, respectively.
At this point, it should be noted that, in a typical dynamic memory, a large number of memory cells is associated with each bit line. For sake of simplicity of discussion, the bit lines are shown with only one or a small number of memory cells.
In addition to the memory cells 100 and 110, the sense amplifier construction of FIG. 1 also requires the use of reference cells, oten called "dummy cells". Unlike memory cells, only one "dummy cell" is typically associated with any given bit line. Dummy cells are indicated by reference numerals 105 and 115 for bit lines 50 and 51, respectively. The dummy cells 105 and 115 are controlled by the word lines 170 and 190, respectively, and have a construction similar to that of memory cells. The charge stored in the dummy capacitor is used as a reference charge with which to compare the charge of the memory cell capacitor.
For a sense operation with the sense amplifier construction of FIG. 1, two bit lines must be used. The first bit line is used to access the memory charge stored in an addressed memory cell, and the second is used to access a reference charge in a "dummy cell". To begin the sense operation, the isolation transistor T.sub.M of an addressed memory cell is turned on by a signal along the appropriate word line 160 or 180. Once the isolation transistor T.sub.M is turned on, the charge on the memory cell capacitor is allowed to transfer to a first bit line. In a similar fashion, the charge on the dummy cell capacitor is allowed to transfer to a second bit line. The resulting differential voltage across the two bit lines is sensed by sense amplifier 10, and is used as an indication of whether the memory cell had stored a logical 1 or a logical 0.
Research and development in semiconductor technology and memory array construction have also produced numerous improvements to dynamic memory arrays. For example, U.S. Pat. No. 4,375,600, issued to Wu, discloses a sense amplifier which employs an FET circuit for amplifying the bit signal which has been attenuated by stray capacitance, and which would otherwise be exceeded by circuit noise voltages. U.S. Pat. No. 4,070,590, issued to Ieda et al, discloses a sensing circuit, wherein power supply transistors are inserted between power sources and bit lines, and separation transistors are inserted between a sense amplifier and each bit line. The power supply transistors allow the signal detection to be performed with little power consumption, and the separation transistors enable the device to have a high-speed and highly sensitive detecting operation. U.S. Pat. No. 4,312,047, issued to Donoghue, discloses a memory array using diode connected transistors to provide isolation between common bit line pairs, and between each bit line and its associated column select circuitry. This improvement produces higher operating speeds and better differential signals for sensing by the sense amplifier. In the 1983, IEEE International Solid-States Circuits Conference publication, dated Feb. 25, 1983, pages 234 and 235, and entitled "Session XVI:256K DRAMs", there is disclosed a construction of a 256K DRAM having an on-chip error checking and correcting (parity) circuit and a threshold difference compensated amplifier.
One improvement, which has been developed with respect to the dynamic memory array of FIG. 1, is that of a shared sense amplifier. This shared sense amplifier approach will be described with reference to FIG. 2 in which the sense amplifier 10 remains the same as in FIG. 1, but is associated with additional bit lines 250, 251, 255 and 256.
Along the bit lines 250, 251, 255 and 256, memory cells 200, 210, 220 and 230 are controlled by the word lines 260, 280, 265 and 285, respectively. Similarly, dummy cells 205, 215, 225 and 235 are controlled by the dummy lines 270, 290, 275 and 295, respectively.
As to the association of the bit lines with the sense amplifier, each of the bit lines 250, 251, 255 and 256 can be connected to the share sense amplifier 10 by the multiplex switches 296, 298, 297 and 299, respectively. In a sense operation with the construction shown in FIG. 2, two of the multiplex switches 296, 298, 297 or 299 are closed such that one bit line can act as a memory cell bit line, and a second bit can operate as a dummy cell bit line. Further discussions of a dynamic memory with a shared sense amplifier construction can be found in the above-cited publication, pages 230 and 231. In addition to the above publication, U.S. Pat. No. 4,351,034, issued to Eaton et al, also discloses a shared sense amplifier arrangement with the additional improvement of utilizing the construction in a folded bit line manner.
This folded bit line improvement can also be illustrated with reference to FIG. 2. In the shared sense amplifier construction shown in FIG. 2, opposite or diagonally opposite bit lines were initially used as a bit line pair. As an example, bit line 250 would be associated with either bit line 251 or bit line 256. This opposite bit line arrangement was found to be undesirable because of circuit noise. Since the bit lines in a associated pair are separated, each bit line is exposed to circuit noise which is different from that of the other bit line. The different noise levels on each of the bit lines may be erroneously sensed as a differential voltage across the bit line pair and, therefore, substantially affect the sensitivity of the sense amplifier. Eaton et al discloses a folded bit line which eliminates this noise problem.
In Eaton et al, bit lines which are closely placed and on the same side of the sense amplifier are chosen as bit line pairs. Thus, for example, in FIG. 2, bit lines 250 and 255 or bit lines 251 and 256 would be chosen as bit line pairs. As the chosen bit line pairs are closely placed, both bit lines are exposed and therefore have the same noise level and waveform induced along each line. As the sense amplifier senses only the differential voltage across a bit line pair, common noise appearing on each bit line will be ignored by the sense amplifier 10. Thus, the folded bit line construction results in an excellent common mode noise rejection ratio.
Although the above prior art has achieved dynamic memories having tremendous capacity and performance characteristics, improvements in dynamic memories have continued to evolve. A recent area of great interest is the dynamic memory array using a dual sense amplifier construction. Recent prior art directed to a dual sense amplifier is the 1983 IEEE International Solid-States Circuit Conference publication, dated Feb. 23, 1983, pages 56, 57 and pages 285 and 286, entitled "Section D-I: CMOS Memory".
A prior art dual sense amplifier construction will be described with reference to FIG. 3 which shows a dual sense amplifier consisting of a P-channel latch 300 and an N-channel latch 305. In contrast to the single sense amplifier construction of FIGS. 1 & 2, the dual sense amplifier construction shown in FIG. 3 utlizes a first half of a sense amplifier spaced at a distance from a second half of the sense amplifier.
Shown disposed between the sense amplifier halves are bit lines 340 and 345, with the first ends of bit lines 340 and 345 being connected to the P-channel latch 300, and the second ends of the bit lines 340 and 345 being connected to the N-channel latch 305. Disposed along the bit lines 340 and 345 are the memory cells 310, 315, 325 and 330 which are controlled by the word lines 360, 370, 380, 390, respectively. Memory cell construction is the same as that which was described with reference to FIG. 1. It should again be noted the number of memory cells along bit lines 340 and 345 in FIG. 3 has been limited for the sake of clarity. In contrast to the previously described single sense amplifier approach, the need for "dummy" reference cells has been eliminated. Thus, there is an absence of "dummy" cells along bit lines 340 and 345 in FIG. 3.
Although the dual latch construction for the sense amplifier can be designed in any MOS technology, this construction is realized particularly well in CMOS (Complementary Metal Oxide Semiconductor) technology. Thus, in a preferred embodiment, CMOS technology is used in the construction of the dual sense amplifier. The operation of the dual sense amplifier memory as shown in FIG. 3 will now be described.
Before a sense operation is begun, the bit lines 340 and 345 are momentarily shorted together by the sense amplifiers halves 300, 305 to insure that the two bit lines are charged to the same voltage level. To sense the state of an addressed memory cell, the appropriate word line is activated to cause the memory cell isolation transistor to turn on and, therefore, transfer the charge of the memory cell's capacitor onto the respective bit line. In addition to the memory cell charge which has been dumped onto the first bit line, the charge on the opposite bit line is also used by the dual sense amplifier as a reference charge. In the sense operation, both the P-channel latch 300 and N-channel latch 305 provide a partial amplification of the sense memory value, one of the latches pulling the more positive line toward the positive supply voltage, and the other latch pulling the more negative line toward the negative supply voltage. The combined effect is a full amplification by the P-channel latch and N-channel latch to provide a full differential power supply level across the two bit lines. The output circuitry of the dual sense amplifier construction is not of importance to the present invention and, therefore, is not shown.
At this point, it is useful to note the differences between the dual sense amplifier construction of FIG. 3 and the sense amplifier construction which were previously described with reference to FIGS. 1 and 2. In contrast to the prior art devices shown in FIGS. 1 and 2, the memory array of FIG. 3 utilizes a dual sense amplifier construction with a P-channel latch spaced apart from an N-channel latch. As each of the dual sense amplifier halves must provide a portion of the total amplification required to complete a sense operation, both sense amplifier halves must be connected to a bit line in order to provide the reqired amplification of the memory value sensed along a given bit line. Thus, the bit lines of FIG. 3 are disposed between the sense amplifier halves, instead of flanking a single sense amplifier construction as shown in FIGS. 1 and 2.
Although the dual sense amplifier memory construction shown in FIG. 3 has been an important development in memory technology, there remains a need for further improvement, as will be discussed below.
As mentioned previously, digital data in a dynamic memory is stored in dynamic memory cells. When a particular memory cell is addressed, a memory cell capacitor C.sub.M is coupled to an associated bit line via an isolation transistor T.sub.M. As a result, a transfer of charge occurs between the memory cell capacitor and the bit line, thereby altering the voltage level on that bit line. In a practical device, the amount of voltage change induced has been found to be dependent on the capacitance along the associated bit line. This bit line capacitance can be attributed to the capacitance of the line itself, and also, to the capacitance due to other memory cells associated with the bit line. This capacitance C.sub.L is illustrated in FIG. 3 as capacitors 301 and 303 for bit lines 340 and 345, respectively.
During the transfer of charge in a sense operation, the memory charge stored in the memory cell capacitor must first be used to satisfy any bit line capacitance before it can induce any voltage change along the associated bit line. The larger the bit line capacitance C.sub.L, the larger the portion of memory charge used to satisfy the bit line capacitance. The larger the amount of memory charge used to satisfy the bit line capacitance, the smaller the change in voltage level induced along that line. Thus, there must be sufficient memory charge stored within the memory cell capacitor C.sub.M with which to satisfy the bit line capacitance C.sub.L, and produce along the bit line sufficient change in voltage which can be sensed and amplified.
As the size of the memory cell capacitor in a practical semiconductor memory is limited, so is the amount of memory charge which can be stored in this memory cell capacitor. Because this limited memory charge must be sufficient to overcome the bit line capacitance C.sub.L and produce sufficient voltage change, the bit line capacitance C.sub.L must not be greater than a certain maximum capacitance value. As the bit line capacitance C.sub.L is determined by both the bit line length and the number of memory cells associated with the bit line, it follows that the combination of bit line length and memory cells associated with the bit line is limited by the practical size limitations imposed on the memory cell capacitor C.sub.M.
Although such limitations still allow bit lines to have a large number of associated memory cells, the greater the number of memory cells that can be associated with a given bit line and sense amplifier, the more efficient the use of expensive semiconductor substrate area. Stated differently, semiconductor memory devices wit greater memory array density can be constructed more cheaply if more memory cells can be associated with a given bit line and sense amplifier. Thus, there exists a need for an approach which will allow a greater number of memory cells to be associated with a given bit line in a memory device utilizing a dual sense amplifier construction.